The present invention relates to a semiconductor memory device having a high capacity and a small size such as a DRAM (i.e., Dynamic Random Access Memory), and a process for fabricating the same.
High-dielectric-constant dielectrics such as Pb(Zr,Ti)O.sub.3 or (PZT) are known to be useful as either a capacitor insulator material for the well-known DRAM memory cells composed of one transistor and one capacitor, or as the ferroelectric layers for a non-volatile memory. A fabrication process using such material is shown in FIG. 1 of IEEE IEDM Technical Digest, pp. 226-270, 1992, for example. High-dielectric-constant dielectrics are formed by the well-known deposition method over the bottom electrodes which are formed separately for the individual cells, and an upper electrode called the plate is then formed. The non-volatile memory uses ferroelectrics sandwiched between the isolated bottom electrodes and the upper electrode, as shown in FIG. 1 of the Journal of Vacuum Science Technology, A, Vol. 10, pp. 1554-1561, 1992.
In the prior art described above, although not explicitly described, the distance between the adjacent capacitors is sufficiently large so that isolation between the adjacent electrodes will not raise a problem, as is apparent from the Figure. On the other hand, in a highly integrated device such as a DRAM of 1 Gbit, which is contemplated by the present invention, isolation widths as small as 0.2 .mu.m or less are used. Therefore, the thickness of the electrodes or dielectrics is as small as the isolation width. This creates a problem in the fabrication and the circuit operation. For example, assume that a structure such as shown in FIG. 2 is formed with an active device layer 201 (in which active devices such as transistors are formed, with appropriate wirings and terminals), a capacitor structure including platinum bottom electrodes 204, a high-dielectric constant insulator 205 and an upper platinum electrode 206, and conductive plugs 202 for connecting the bottom electrodes 204 with devices in the layer 201. If this structure is formed, for example, with such small isolation widths, the coupling capacitance between the adjacent bottom electrodes 204 becomes higher than the capacitances of the upper electrode 206 and the bottom electrodes 204, thus apparently causing instabilities in the circuit operation.
FIG. 13 shows how the lateral leakage current significantly increases with a decrease in the distance between electrodes. As illustrated there, when the distance between adjacent electrodes is greater than 1 .mu.m, the lateral leakage current is not especially large. On the other hand, as the spacing approaches 0.2 .mu.m, the lateral leakage current greatly increases to the point of being a significant concern. As noted earlier, it is now desired to form such compact devices with electrode spacing of 0.2 .mu.m or less, and, accordingly, steps must be taken to minimize the leakage current to produce an optimized device.
For solving the above problems, it is effective to retain the step coverage by using a high-dielectric-constant layer forming method including Chemical Vapor Deposition, and by cutting the electric coupling between the adjacent bottom electrodes 304 by forming the structure shown in FIG. 3. Particularly, in this structure, high-dielectric constant layers 305 are individually formed over each bottom electrode 304. In this case, however, stable operation is difficult to obtain because the working space for removing the high-dielectric-constant dielectrics from the bottom of the trench is as small as 0.1 .mu.m or less and has a high aspect ratio.
Therefore, it is preferable to form the structure such that removal of the high-dielectric constant material from the trench bottom is unnecessary, as shown in FIG. 4. However, Chemical Vapor Deposition of a high-dielectric-constant material 405 such as PZT containing lead as its component element is characterized in that the composition of the deposited layer is influenced by the material of the underlying layer. Although the bottom of FIG. 4 contains a silicon oxide as its major component, the electrode portions 404 are made of platinum so that the dielectrics containing excessive lead are deposited on the bottom if the bottom and the electrode surface are simultaneously subjected to the deposition. As a result, problems are caused by the DC leakage current between the adjacent electrodes 405 or the deterioration of morphology.
One reason for the increase in leakage current in the presence of excess lead is the decrease in breakdown voltage which such excess lead can cause. FIG. 14 provides an illustration of the changes in breakdown voltage and normalized dielectric constant based upon the amount of excess lead. As can be appreciated from FIG. 14, as the amount of excess lead increases, the breakdown voltage drops dramatically, to a point where it is practically 0 volts.